Job Description: As a member of Concept Engineering Hardware Architecture team that specifies the solutions for 2.5G and 3G handset baseband chips, the candidate will be responsible for the Digital Baseband portion of the solution. This includes the overall HW architecture meeting the functionality and performance specified by the System Requirements. The candidate would be responsible for generating the Subsystem Requirements, allocating the system requirements to the different baseband subsystems of the solution and specifying the implementation architecture to meet the requirements. The responsibilities of the Hardware Architect include some or all of the following:
*Definition of Digital Baseband HW architecture
Deep understanding of ARM/DSP based SoC architectures, bus architectures, peripherals, and security features.
Ability to design, implement, and simulate system models for architecture tradeoff and bandwidth analysis
The candidate will also be expected to:
Comprehend and communicate competitor Digital Baseband architectures and capabilities.
Develop System Functional specifications that will be used to guide the Development organizations during product development.
Generate system level requirements for the Digital Baseband portion of a product based on Marketing Requirements Document and industry norms.
Willing to travel international to Germany is required.
Bachelors degree in Electrical Engineering
3 years engineering experience
3 years experience with ARM based SoC architecture solutions
Masters degree in Electrical Engineering
3 years experience and understanding of GSM/GPRS/UMTS Handset systems
3 years experience and understanding of IC design, simulation, and testing methodologies
Understanding of Mobile handset system architectures including:
o Analog baseband HW architectures and interfaces
o Power management IC HW architectures and interfaces
o Radio/RF HW architectures and interfaces
o Knowledge of external component functionality and interfaces: memory, display, camera, external memory cards, connectivity (USB, BT, etc.)
Understanding of power savings techniques, technology, and algorithms
o Ability to review and analyze process technologies and process options in support of low power design
o Understanding of low power IC design architectures and system design architectures.
Understanding of IC design process and designs
o Process technologies, standard cell libraries, memories, PLLs, clock generation, I/O buffers
Experience Required3 years