We are looking for an individual to fill a position for a logic verification engineer. Candidates will be performing ASIC verification based on architectural/micro-architectural specification review and analysis followed with definition of verification requirements. The person in this position will also have the following responsibilities: Develop tests and test bench components from high level verification plans, as well as debug of failing tests, definition of functional coverage space, implementation of coverage monitors and analysis of test coverage space, regression running and debugging failing tests, design and development of test bench collateral. Team members will also work closely with design and architecture teams to review and refine test and coverage requirements. Good interpersonal skills and the ability to work in a highly cooperative team environment across many time zones.
You must possess a minimum of Bachelors or Masters Degree in Electrical Engineering or Computer Engineering.
1+ years experience object oriented software skills with experience using 1 or more of the following languages: System Verilog/Verilog, Perl, C/C++
Some experience with RTL simulators, VCS preferred
Experience of specifying and developing test bench components, specifying developing, and debugging functional tests, and specifying, implementing and analyzing functional coverage
Strong debug abilities is an advantage
Experience Required1+ years